(Sr) ASIC DFT Engineer
As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:
1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.
2、Block level dft drc check & fix it in RTL/Netlist level.
3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.
4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.
1、Hand on experience of SoC DFT implementation, Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnose.
2、 Expertise with Mentor/Synopsys DFT tools.
3、 Expertise with DFT advisor tools.
4、 Experience in MBIST/SCAN/ATPG Pattern simulation and debug on RTL & Netlist.
5、 A high-level of self-motivation and a proactive approach to solving problems.